1. Field of the Invention
The present invention generally relates to a test device for testing a package-on-package (PoP) stacked-chip; in particular, the present invention relates to a test device including a test head having a top chip of a PoP stacked-chip installed inside, for testing a bottom chip of the PoP stacked-chip.
2. Description of Related Art
Currently available portable electronic products like smartphones, mobile computing products and various electronic consumer devices all seek higher semiconductor functionalities and performance under the conditions of limited occupation areas and least thickness and weight with the lowest fabrication costs, so certain manufacturers have recognized such trends and devoted efforts specifically on the integration of semiconductor chips, and also developed three-dimensional packaging technology such as die stacking and package stacking.
The package stacking can be generally categorized into two types, respectively referred as package-on-package (PoP) and package-in-package (PiP). More specifically, in terms of the integral structure of PoP, at present, the technology utilized in industry can lay out more than one hundred contacts on a single chip of square centimeter area, which typically comprises a two-layer structure consisting of a first package (top package) and a second package (bottom package), wherein the first package (top package) is stacked on top of the second package (bottom package), with each package surface including more than one hundred micro contacts (solder balls) for soldering connection, and then the contacts respectively on the first package and the second package are mutually connected by means of precision soldering technologies. So far, the chip-under-test fabricated in this way is still individually inspected all through visual and manual test operations. In the PoP stacked-chip, upon stack integrating the top chip with the bottom chip, it is necessary to perform test processes on final test yield. Therefore, in a conventional stacked-chip package, it is required to manually place an individual top chip onto an individual bottom chip in stack, and then press down the test arm to abut against the surface of the top chip already stacked on top of the bottom chip so as to perform the final test. However, in case that low yields or continuous errors do occur from the test results, it may become difficult to clearly differentiate whether the top chip or the bottom one causes such problems. Seeking other approaches for solution may complicate the entire process, if unable to efficiently identify the problem source.